Task Mapping with Cache Reconfiguration and Partitioning for Energy Minimization on Real-Time Multicores

In this paper, we investigate the problem of task mapping with Dynamic Cache Reconfiguration (DCR) and Cache Partitioning (CP) which are promising techniques to alleviate cache energy consumption. Our goal is to obtain an optimal task mapping, L1 cache configuration and L2 cache partition factor on a target multi-core architecture such that cache energy consumption is minimized while timing constraints is satisfied. Two approaches are presented to solve this problem: the first optimal approach is based on integer linear programming (ILP), whereas the second approach is a genetic algorithm (GA) that is near-optimal, but scalable. Experimental results show that our ILP based approaches can find the optimal task mapping, leading to significant energy reduction, and the computation time is tolerable. Moreover, our GA can also find a near-optimal solution with little time overhead.